Many integrated systems require a fixed voltage, or reference voltage, with accuracy to a fraction of a percentage. With the advancement of technology, the sampling rate of sample data systems has increased, causing the number of times in which a reference voltage is used in a period of time to increase as well.
Each time a reference voltage is used, an amount of charge is removed from the reference voltage, causing the reference voltage level to decrease in value. Preferably, this decrease in voltage level is compensated for at a fast enough rate so that the reference voltage will maintain its constant level, and be stable and reasonably noise-free, before being sampled again.
Several approaches have been employed to accomplish such a constant level. One approach is not to try to settle the voltage level during the allocated sampling time, but instead. to simply use a single stage low gain amplifier with an external capacitor large enough so that the change in reference voltage, on a per sample bases, is negligible. unfortunately, this method presents no means of recharging the reference voltage to compensate for the current drawn from the reference voltages, thereby causing a DC error in the reference voltages which, in turn, causes a gain error in the sample data system.
Rather than use a large capacitor in the attempt to alleviate the dramatic effects of a reference voltage drop, other methods attempt to completely restore the reference voltage between each sampling. These methods tend to utilize very high speed, on chip amplifiers in order to settle the reference voltages between each sampling, which could potentially be less then 5 ns. While this method does keep the reference voltage constant, it also burns an enormous amount of power and requires a large amount of excess circuitry to perform the voltage settling.
Therefore, there is a need in the art for an accurate, low power approach of maintaining a reference voltage level regardless, of the sampling speed of the system upon which it is utilized.